This application relies for priority upon Korean Patent Application No. 97-54216, filed on Oct. 22, 1997, the contents of which are herein incorporated by reference in their entirety.
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to an insulated gate bipolar transistor (IGBT) and a method of manufacturing the same.
2. Description of the Related Art
Recently, demands have rapidly increased for an inverter used in a logic circuit for a robot or machine tool, an inverter used in industrial electronics as a power device without power failure for office supplies, and an inverter used in a small power converter for the public. In the specific case of a power converter, together with any extension of this application field, the need has increased for a small and light power converter with low noise that provides a high efficiency. However, conventional semiconductor devices such as bipolar junction transistors (BJTs) or a high-power MOS field effect transistors (MOSFETs) cannot satisfy such requirements. Thus, a new semiconductor device has been developed that has both the high-speed switching characteristic of a MOSFET and the high power characteristic of the BJT. This device, an insulated gate bipolar transistor (IGBT), has now become the object of much attention.
The IGBT has a latch-up phenomenon in that the current cannot be controlled by the gate voltage if the current increases. Such latch-up phenomenon is the primary factor for limiting the level of current that enables operation of the IGBT.
In an IGBT having a thyristor structure, if a hole current flowing beneath an n+ source region formed on a pxe2x88x92 well increases, the voltage between the well and the source region is decreased by the resistance of the pxe2x88x92 well. If this difference in voltage is over a predetermined level, a parasitic npnp thyristor comes into operation. When the thyristor operates, it provides an electron current to a pnp transistor. Thus, even if the gate voltage is blocked, the current level is increased via the pnp transistor, rather than the pnp transistor turning off. As a result, the temperature of the IGBT increases, leading to the breakdown of the IGBT.
These serial operations refer to the latch-up phenomenon. In order to prevent this latch-up phenomenon, the controllable current level is increased and an accumulated carrier is rapidly removed at the same time for a high-speed operation. This is a key for making the IGBT practical.
On the other hand, when a power semiconductor device is used to drive a motor, a saturation current, which is about 4xcx9c5 times higher than the actual operation current, flows if the motor is overloaded. Because of the heat generated by this much current, the efficiency of the emitter in a power semiconductor device increases. As a result, many holes are injected into the semiconductor device, resulting in a latch-up phenomenon. This phenomenon is called a xe2x80x9cshort circuit currentxe2x80x9d or a xe2x80x9cthermal latch-upxe2x80x9d.
Many suggestions have been provided to supply a large current by preventing the above latch-up phenomenon. Particularly, a structure has been widely used in which a p+ well is formed in a pxe2x88x92 well using an ion implantation method. A conventional IGBT having such a structure will be described briefly with reference to FIGS. 1 through 3.
FIG. 1 is a layout of a conventional IGBT capable of preventing the latch-up phenomenon.
As shown in FIG. 1, reference numeral 100 represents a first mask pattern for forming a gate electrode; reference numeral 110 represents a second mask pattern for forming a p+ well region to remove the latch-up; reference numeral 120 represents a third mask pattern for forming a n+ source region; and reference numeral 130 represents a mask pattern for forming a contact hole that connects a metal electrode with the source region and well region formed in a semiconductor substrate, respectively.
FIGS. 2 and 3 are section views of the conventional IGBT shown in FIG. 1, cut along line II-IIxe2x80x2 and line III-IIIxe2x80x2, respectively.
Referring to FIGS. 2 and 3, an n+ buffer layer 4 with a high concentration is formed over a p+ semiconductor substrate 2. Also, an nxe2x88x92 semiconductor layer 6 with a low concentration is grown over the n+ buffer layer 4 by an epitaxial growth method. A gate electrode 10 made of a polysilicon layer is formed over the nxe2x88x92 semiconductor layer 6 while a gate dielectric film 8 is interposed between the gate electrode 10 and the nxe2x88x92 semiconductor layer.
A pxe2x88x92 well region 12 is formed by impurity ion implantation and thermal diffusion beneath the surface of the nxe2x88x92 semiconductor layer 6, between the gate electrodes 8. Also, in order to prevent the latch-up, a p+ well region 14 with a high concentration is formed by ion implantation and thermal diffusion, passing through the center of the pxe2x88x92 well region 12 (see FIG. 2) and extended to a part of the nxe2x88x92 semiconductor layer 6.
Also, an n+ source region 16 is formed beneath the surface of the pxe2x88x92 well region 12 and the p+ well region 14 using a mask for the source. A metal electrode 20 used as a cathode is formed on the surface of the n+ source region 16 and p+ well region 14. Here, reference numeral 18 represents a dielectric film for electrical insulation between the metal electrode 20 and the gate electrode 10.
In the conventional IGBT described above, the resistance between the pxe2x88x92 well region 12 and the n+ source region 16 is decreased by the p+ well region 14, which is formed to pass through the pxe2x88x92 well region 12. Thus, the difference in voltage between the source region 16 and the well regions 12 and 14 is decreased, thereby improving the latch-up phenomenon.
However, according to the above conventional IGBT, electron current and hole current both flow in the same direction, collecting in an emitter contact where the metal electrode 20 contacts the n+ source region (see FIG. 3). Thus, if the concentration of the pxe2x88x92 well region 12 is low, the hole current is multiplied by the resistance of the pxe2x88x92 well region, thereby causing a voltage drop in the pxe2x88x92 well region 12 beneath the n+ source region 16. As a result, it is difficult to prevent the latch-up of the IGBT, and the short circuit current characteristics of this circuit are deteriorated.
To solve the above problems, it is a first object of the present invention to provide an insulated gate bipolar transistor (IGBT) that is capable of improving the control of latch-up and short circuit current characteristics.
It is a second object of the present invention to provide a method for manufacturing this IGBT.
To achieve the first object, there is provided an insulated gate bipolar transistor (IGBT). In the IGBT, a semiconductor layer of a second conductive type is formed over the semiconductor substrate. A well of the first conductive type is then formed beneath the surface of the semiconductor layer. A source region of the second conductive type is formed in the well and doped with a high concentration. And a gate electrode is formed over the semiconductor layer. The gate electrode only contacts the source region outside of a cathode region in which a contact between the source region and a cathode electrode is formed.
Preferably the IGBT also comprises an impurity region of the first conductive type for controlling latch-up, the impurity region being extended to a part of the primary semiconductor layer via the well. The IGBT may also comprise a highly-doped semiconductor layer of the second semiconductor type, formed over the semiconductor substrate. The IGBT may also comprise an impurity region of the first conductive type for controlling latch-up, the impurity region being extended to a part of the primary semiconductor layer via the well.
In addition, the IGBT may comprise an interlayer dielectric (ILD) film formed over the gate electrode, and a cathode electrode electrically insulated from the gate electrode by the ILD film, and connected to the source region and the well.
The first conductive type may be p-type and the second conductive type n-type, or the first conductive type may be n-type and the second conductive type p-type.
According to an aspect of the second object, there is provided a method for manufacturing an insulated gate bipolar transistor (IGBT), comprising the steps of forming a primary semiconductor layer of a second conductive type over a semiconductor substrate of a first conductive type, forming a plurality of gate electrodes over the primary semiconductor layer, the plurality of gate electrodes being separated by a predetermined distance, forming at least one well of a first conductive type in the primary semiconductor layer, between the plurality of gate electrodes, and forming a source region of a second conductive type in the well, wherein the source region only contacts the gate electrode outside of an emitter contact region.
The method for manufacturing an IGBT may also comprise the step of forming a highly-doped semiconductor layer of the second conductive type over the semiconductor substrate. This step is preferably performed before the step of forming a primary semiconductor layer of a second conductive type over a semiconductor substrate of a first conductive type.
The method for manufacturing an IGBT may also comprise the steps of forming a gate dielectric film over the primary semiconductor layer, forming a conductive layer over the gate dielectric film, and patterning the conductive layer and the gate dielectric film in the emitter contact region. The conductive layer and the gate dielectric film are preferably separated from the source region by a predetermined distance.
In addition, the method for manufacturing an IGBT may comprise the step of forming an impurity region in the primary semiconductor layer adjacent to the source region and passing through the well, the impurity region operating to control latch-up. This step is preferably performed before the step of forming a source region of a second conductive type in the well.
The method for manufacturing an IGBT may also comprise the steps of forming an insulation film over the source region, forming a contact hole to expose the well and the source region by partially etching the insulation film, and forming a cathode electrode connected to the source region and the well by forming a metal layer over and in the contact hole. These steps are preferable performed after the step of forming a source region of a second conductive type in the well.
The first conductive type is preferably p-type and the second conductive type is preferably n-type. Preferably, the semiconductor layer is formed by an epitaxial growth method.
According to another aspect of the second object, there is provided a method for manufacturing an insulated gate bipolar transistor (IGBT), comprising the steps of forming a primary semiconductor layer of a second conductive type over a semiconductor substrate of a first conductive type, forming a plurality of patterned conductive layers for a gate over the semiconductor layer, the plurality of conductive layers being separated from each other, forming a well of the first conductive type over the semiconductor layer between the plurality of conductive layers, forming a source region of a second conductive type in the well, each side of the source region being adjacent to one of the plurality of conductive layers, and forming a gate electrode having a region separated by a predetermined distance from the source region by partially etching the plurality of conductive layers.
The method for manufacturing an IGBT preferably comprises the step of forming a highly-doped semiconductor layer of the second conductive type over the semiconductor substrate. This step is preferably performed prior to the step of forming a primary semiconductor layer of a second conductive type over a semiconductor substrate of a first conductive type.
The method for manufacturing an IGBT may also comprise the step of forming an impurity region of the first conductive type in the primary semiconductor layer adjacent to the source region and passing through the well, the impurity region operating to control latch-up. This step is preferably performed before the step of forming a source region of a second conductive type in the well.
The method for manufacturing an IGBT may also comprise the steps of forming an insulation film over the source region, forming a contact hole that exposes the well and the source region by partially etching the insulation film, and forming a cathode electrode connected to the source region and the well by forming a metal layer over and in the contact hole. These steps are preferably performed after the step of forming a gate electrode.
The first conductive type is preferably p-type and the second conductive type is preferably n-type. Preferably, the semiconductor layer is formed by an epitaxial growth method.